The present invention relates generally to semiconductor devices and more particularly to apparatus and methods for reducing imprint in ferroelectric memory cells.
In semiconductor memory devices, data is read from or written to the device using address signals and various other control signals. Such memory devices are used for storage of data and/or program code in personal computer systems, embedded processor-based systems, and the like. Ferroelectric memories are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) configurations, which are well known. The ferroelectric memory cells typically comprise one or more ferroelectric (FE) capacitors adapted to store a binary data bit, as well as one or more access transistors, typically MOS devices, operable to selectively connect the FE capacitor to one of a pair of complimentary bitlines, with the other bitline being connected to a reference voltage. The individual cells are commonly organized as individual bits of a corresponding data word, wherein the cells of a given word are accessed concurrently by activation of platelines and wordlines by address decoding circuitry.
Ferroelectric memory devices provide non-volatile data storage where data memory cells are constructed using ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within Perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field which exceeds the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles. The response of the polarization of a ferroelectric capacitor to the applied voltage may be plotted as a hysteresis curve.
Data in a ferroelectric data cell is read by connecting a reference voltage to a first bitline and connecting the cell capacitor between a complimentary bitline and a plateline signal voltage. This provides a differential voltage on the bitline pair, which is connected to a sense amp circuit. The reference voltage is typically supplied at an intermediate voltage between the voltage associated with a capacitor charged to a binary xe2x80x9c0xe2x80x9d and that of the capacitor charged to a binary xe2x80x9c1xe2x80x9d. The polarity of the sensed differential voltage thus represents the data stored in the cell, which is buffered and applied to a pair of local IO lines. The transfer of data between the ferroelectric memory cell, the sense amp circuit, and the local data bitlines is controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry in the device.
Connection of the ferroelectric cell capacitor between the plateline and the bitline during a read operation causes an electric field to be applied to the cell capacitor. If the field is applied in a direction to switch the internal dipoles, more charge will be moved than if the dipoles are not reversed. As a result, sense amplifiers can measure the charge applied to the cell bit lines and produce either a logic xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d at the sense amp terminals. Since reading the cell data is a destructive operation, the sensed data is then restored to the cell following each read operation. To write data to the cell, an electric field is applied to the cell capacitor to polarize it to the desired state. Ferroelectric memories provide certain performance advantages over other forms of non-volatile data storage devices, such as flash and EEPROM type memories. For example, ferroelectric memories offer short programming (e.g., write access) times and low power consumption.
However, ferroelectric memories suffer several shortcomings, which have heretofore inhibited their widespread acceptance in the marketplace. Among these are memory cell relaxation and imprint phenomena associated with the ferroelectric capacitors used in forming the.memory cells. Relaxation involves partial loss of charge from the ferroelectric capacitor where a cell is unaccessed in a period shortly after a sequence of continuous cycling of the cell. Imprint is the tendency of ferroelectric capacitors to prefer one state over the other, which is found where the cell capacitor is programmed to one state for a long period of time. The hysteresis curve for an imprinted cell capacitor effectively shifts to favor the stored state due to a charge build-up. In a ferroelectric memory device, cell imprint results in a voltage offset in both the xe2x80x9c0xe2x80x9d state voltage and the xe2x80x9c1xe2x80x9d state voltage, and hence reduces the sensing margin with respect to the reference voltage to which the cell voltage is compared during a read operation.
As a result, ferroelectric cell imprint may cause an undesirably low signal level being presented to the sense amps during read operations. This, in turn, leads to the possibility of device failure during testing, or the potential provision of erroneous data during a memory device read. Thus, there is a need for improved ferroelectric memory devices and methodologies by which the adverse effects of imprint phenomena may be mitigated or reduced.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
One aspect of the invention relates to ferroelectric memory devices in which the data stored in individual ferroelectric memory cells is inverted during or following a read operation. The invention may be employed to mitigate or reduce imprint phenomena associated with ferroelectric cell capacitors in such devices. Toggle memory cells are provided for storing toggle data bits associated with data words, which indicate whether the data cell data is currently stored in an inverted state or in a non-inverted state. During a read operation, the toggle data bit information is used to selectively invert data being provided to local IO lines or to sense amp circuits if the data was stored in the inverted state. In applications where data in cells corresponding to a data word is read more frequently than it is written, the invention may reduce the adverse effects of cell capacitor imprint by reversing the programmed state of the cell capacitor each time the cell is read, even though the actual cell data has not changed. The toggle data thus provides an indication of whether sensed cell data is actual or inverted, which may be used during transfer of sensed cell data to IO lines or during sensing operation, to re-invert data as needed. Thus, the local IO lines are always provided the correct data, regardless of whether the sensed cells contained inverted or non-inverted data.
Another aspect of the invention provides methods for reading data from a ferroelectric data memory cell in a memory device, comprising sensing a data bit from a data memory cell and sensing a toggle bit from a toggle memory cell. The method further comprises selectively inverting the data bit sensed from the data memory cell according to the sensed toggle bit, and transferring the data bit to an IO line. The method may also be employed in restore operations involving inverting the data bit and transferring the inverted data bit to the data memory cell and inverting the toggle bit and transferring the inverted toggle bit to the toggle memory cell during a restore operation.